1. Field of the Invention
This invention relates generally to semiconductor devices having different metallization thicknesses on different portions of the device surface, and, more particularly, to semiconductor integrated circuits having a thin patterned metal over a portion of a circuit having a complex metal pattern and a thick patterned metal over a portion of the circuit having a relatively simple metal pattern.
2. Brief Description of the Prior Art
In the past, semiconductor devices and integrated circuits have generally been made with a single-thickness metal interconnect pattern for electrically linking all the components in the substrate. Many integrated circuits, however, combine control circuitry and power devices on the same substrate. As the dimensions of the components have shrunk and the current-carrying demands on the power devices have escalated with advances in the state of the art, it has become highly desirable to use at least two thicknesses of metal in such circuits. A relatively thin layer of metal is deposited over the complex portion of the circuit, such as the control circuitry. The relatively thin metal facilitates patterning into the relatively fine lines required to maintain a high density in the low-power portion of the integrated circuit. A substantially thicker metal is deposited and patterned over the power output or high current portion of the integrated circuit. Here there is less requirement for very fine lines but a substantially thicker metal is deposited and patterned over the power output or high current portion of the integrated circuit. Here there is less requirement for very fine lines but a substantial need to minimize internal voltage drops which waste power and disturb the current distribution within the power device.
In the past, such a dual-thickness metallization scheme has been implemented by a sequence of deposition and patterning steps. First, a thin layer of metal is deposited and patterned to form the interconnects over all of the circuit. Then, an insulator layer, typically chemical vapor deposited oxide, is put down over the first layer of metal and patterned to expose those portions of the first layer metal pattern which needs to be contacted by the thicker layer. Then the thicker layer of metal is deposited and patterned to leave it only in the desired regions. Thus, a total of three deposition steps and three patterning steps have been utilized to provide a dual-thickness metallization scheme. Such a scheme is expensive, and in addition leads to other problems, such as the mechanical strength of the thick-metal portions over the deposited oxide.
Thus, a need has existed for a better structure and process suitable for providing at least two different metallization thicknesses in two or more different portions of a semiconductor device or integrated circuit without incurring the relatively high cost or poor performance of known systems.